Along with the tendency of higher density and higher speed of semiconductor devices, some measures have been suggested to cope with the delay of access time due to the increase of capacity. For example, in an address buffer and decoder circuit, the number of memory gates to be driven and the parasitic capacitance are increased with an increase of memory capacity and the increase of the number of divided memory arrays. Therefore, high operation speed from the address buffer to the decoder is achieved by adoption of an address predecoder circuit and by suppressing of the parasitic capacitance. The address predecoder circuit ensures high speed performance by using predecoder signals for the input of the decoder and reducing the input capacity.
In a conventional semiconductor memory device adopting the predecoder circuit, an address transition detection (ATD) pulse is supplied to an I/O line precharge circuit to precharge the input 1 output lines during the ATD pulse time period, and sets the predecoder to be enabled upon ending of the ATD pulse, because a pair of input 1 output lines are to be fully precharged and equalized prior to transferring a pair of data bits to the pair of input and output lines, in order to accurately and swiftly transfer a pair of data bits without any errors. The predecoder is simultaneously enabled with the end of the ATD pulse to combine the outputs of the address buffer, and the combined outputs are finally combined by a main decoder, so that an input/output gate is selected to perform the data transmission. The ATD pulse is fed and precharged to the precharge circuit of the input and output lines before the ATD pulse is ended, then the predecoder waits until the ATD pulse is ended. Thereafter, the predecoder is enabled to combine the output of the address buffer, and the input/output gate is finally selected by the main decoder.
As a result, the whole access time of the column address is represented by the sum of the holding time of the ATD pulse and the decoding times of the predecoder and the main decoder. Accordingly, the access time of the column address is delayed as much as the holding time of the ATD pulse. It is possible to shorten the width of the ATD pulse in order to reduce the access time of the column address, but such has practical limitations. In other words, the ATD circuit is serving as a means for detecting the rising edge of the address signal and generates a pulse having a delayed time width by exclusively oring the original address signal and the delayed address signal, so that it is difficult to shorten the width of the pulse less than 10 ns due to the circuit requirements.